Timing calibration pattern for SLDRAM

ABSTRACT

Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2 N  bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

FIELD OF THE INVENTION

The present invention relates to an improved binary calibration pattern which is useful for calibrating timing of control and data signals in SLDRAM memory devices.

DISCUSSION OF THE RELATED ART

Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to EDO to SRAM to DDR SDRAM to SLDRAM, the latter of which is the subject of much current industry interest. SLDRAM has a high sustainable bandwidth, low latency, low power, user upgradability and support for large hierarchical memory applications. It also provides multiple independent banks, fast read/write bus turn-around, and the capability for small fully pipelined burst.

One characteristic of SLDRAM is that it uses both the positive- and negative-going edges of a clock cycle to READ and WRITE data to the memory cells and to receive command and FLAG data from a memory controller.

An overview of SLDRAM devices can be found in the specification entitled “SLDRAM Architectural and Functional Overview,” by Gillingham, 1997 SLDRAM Consortium (Aug. 29, 1997), the disclosure of which is incorporated by reference herein.

Because of the required high speed operation of SLDRAM, and other contemporary memory devices, system timing and output signal drive level calibration at start-up or reset is a very important aspect of the operation of such devices to compensate for wide variations in individual device parameters.

One of the several calibration procedures which is performed in current SLDRAM devices is a timing synchronization of clock signals CCLK (command clock signal) and DCLK (data clock signal) with data provided on an incoming command path CA and FLAG path (for the CCLK signal) and on the data paths DQ (for the DCLK signal) so that incoming data is correctly sampled. Currently, a memory controller achieves this timing calibration at system initialization by sending continuous CCLK and DCLK transitions on those clock paths and transmitting inverted and non-inverted versions of a 15 bit repeating pseudo random SYNC sequence “111101011001000” on each of the data paths DQ, the command path CA, and the FLAG path. The SLDRAM recognizes this pseudo random sequence by two consecutive ones “1” appearing on the FLAG bit and determines an optimal relative internal delay for CCLK and DCLK to optimally sample the known bit pattern. This optimal delay is achieved by adjusting the position of the received data bits to achieve a desired bit alignment relative to the clock. This is accomplished by adjusting a delay in the receiving path of the received data until the received data is properly sampled by the clock and recognized internally. Once synchronization has been achieved, that is, the proper delays on the data receiving paths have been set, the memory controller stops sending the SYNC pattern and the SLDRAM, after all calibrations are completed, can be used for normal memory READ and WRITE access.

While the timing calibration described above, which is conducted at start-up and reset, has been found to perform adequately in most circumstances, there is a problem in that current SLDRAM devices capture incoming data on both positive and negative going transitions of the clock signals CCLK and DCLK As a consequence, even when timing calibration is achieved it is not clear if alignment was achieved on a positive going or negative going clock edge. That is, the 15-bit synchronization pattern lacks any timing signature. It would be preferable to always align the data timing on one of the positive or negative going edges, e.g., the positive going edge, to simplify the command bit logic circuit. If circuit designers simplify the command bit logic circuit on the assumption that alignment is achieved on one of the positive and negative going edges, e.g., positive going edge, of the clock signal, achieving timing synchronization using the current 15 bit pseudo random pattern cannot guarantee that synchronization was achieved with respect to the correct, e.g., positive going, clock edge. If, for example, synchronization was achieved on the negative going edge of a clock signal when the circuitry is designed on the assumption that synchronization is achieved on a positive going edge, when data is later sampled during memory access the data sampling may be off by one bit. Moreover, because the 15-bit pseudo random pattern is repeated during the calibration process, there will be alternating times when it is properly synchronized on the correct clock transition, e.g., positive going, and then improperly synchronized with, e.g., a negative going transition, and there is no mechanism for knowing when the calibration process is completed, whether synchronization has been achieved in the positive or negative going transition of the clock. Thus, calibration may be achieved in the wrong phase of the clock signal, leading to incorrect sampling of the data during memory access operations, or requiring additional complicated circuitry to ensure that incoming data is synchronized to the proper phase of the clock.

Another weakness of the 15-bit synchronization pattern is associated with how calibration is carried out. When one data path is calibrated, an inverted version of the 15-bit pattern is delivered to pins/data paths adjacent to the data path being calibrated so that calibration can occur in the presence of out-of-phase cross talk on adjacent paths. However, only out-of-phase cross talk calibration is achieved for any given data path.

SUMMARY OF THE INVENTION

The present invention is designed to overcome the possibility of achieving synchronization on an undesired phase of the data clock. To this end the invention provides a 2^(N) bit synchronization pattern which, because it has an even number of bits, will ensure that incoming data synchronization is always achieved in a desired phase of the associated clock. The synchronization pattern is preferably a 2^(N) bit pattern which is achieved by adding an additional bit to a 2^(N)−1 pseudo random bit pattern. The synchronization bit pattern employed in the invention is also preferably 16 bits long.

In addition, during calibration of one data path, adjacent data pins and/or data paths are fed with both in phase and out of phase versions of the 2^(N) bit calibration pattern so that calibration operations take place in the presence of both in phase and out of phase cross talk on adjacent data pins and/or paths.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages and features of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings in which:

FIG. 1 illustrates an SLDRAM bus topology with which the invention is used;

FIG. 2 illustrates a portion of the SLDRAM module shown in FIG. 1;

FIG. 3 illustrates a simplified timing diagram illustrating a portion of the timing signals used in the operation of the FIG. 2 circuit;

FIG. 4 illustrates a graphic example of the synchronization technique used to synchronize the SLDRAM system of FIG. 1;

FIG. 5 illustrates a pattern of acceptable delay values for synchronization used in the invention;

FIG. 6 is a representative circuit for generating a 2^(N) 16-bit code used in the present invention;

FIG. 7 illustrates all acceptable delay values for synchronization under various possible cross talk conditions; and

FIG. 8 illustrates a processor based system using an SLDRAM memory which employs calibration structures and process methodologies in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A SLDRAM system which employs the invention is illustrated in FIG. 1. It includes a plurality of SLDRAM modules 11 a . . . 11 n which are accessed and controlled by a memory controller 13. Memory controller 13 provides a command link to each of the SLDRAM modules 11 a . . . 11 n which includes a clock signal CCLK on inverted and non-inverted clock signal paths, a 1 bit FLAG signal and a 10 bit command bus CAO-9. In addition, SLDRAM input/output signals SO, SI are provided from memory controller 13 in daisy chain fashion to the SLDRAM modules 11 a . . . 11 n. In addition, a bi-directional data bus DQO-17 is provided between memory controller 13 and each of the SLDRAM modules 11 a . . . 11 n, as are bi-directional data clocks DCLKO and DCLK1. The clock DCLKO is used to strobe input/output data into and out of the SLDRAM modules, a process for which the DCLK1 signal path is also intermittently used.

FIG. 2 illustrates a simplified relevant portion of one of the SLDRAM modules 11 a . . . 11 n. It includes a control logic circuit 21, latches 23, 25, 49, 59, delay devices 27, 29, 31, 55, 57 which may be ring delay devices, buffers 35, 37, 39, 33, 45, 47, 51, 53, a delay lock loop 41, multiplexer 43, pipeline circuits 61, 63, SRAM input/output circuits 65 and 67, and respective memory banks Bank0 and Bank1 69, 71. It should be noted that although two memory banks are illustrated in FIG. 2, this is just illustrative, as any number of memory banks can be used.

Control logic circuit 21 receives and analyzes commands on the CAO-9 bus and controls the input/output (I/O) access operations of the memory banks 69, 71. The control logic circuit 21 also receives the FLAG signal and the clock signal CCLK.

The signals on each of the command bus paths CAO-9 are passed through respective adjustable ring delay circuits 27 and into respective latches 23 where the signals are latched by a CCLK signal, as buffered by buffer 39, delayed by delay 31 and buffered by buffer 33.

The signal CCLK also passes from buffer 39 into a delay lock loop circuit 41 which provides 16 clock signals into a multiplexer 43. The multiplexer provides 18 clock output signals through respective buffers 45 to 18 latches 49 which latch data output from the memory banks 69, 71. The output data from memory banks 69, 71 pass into SRAMS 65,67 which act as I/O buffers and pass through pipeline circuit 61 before being loaded into latches 49. The output data latched in latches 49 is provided to respective buffer amplifiers 47 and from there is passed back to memory controller 13 via data bus DQ.

Data which is to be input to memory banks 69, 71 is supplied by memory controller 13 on the DQ data bus, is passed through gated buffers 51 through ring delays 57 on each path of the data bus, into latches 59, through pipeline circuit 63. From pipeline circuit 63, input data on the DQ bus passes into buffer SRAM 65, 67 and into a memory bank 69, 71.

The control logic circuit 21 also issues an enable command RXEN whenever the memory controller indicates a memory access WRITE operation by way of a WRITE command in the data on the command bus CAO-9. The RXEN command enables the data input buffers 51 and a data clock input buffer 53. The data clock DCLK passes through gated buffer 53, delay circuit 55 and is used to control latch 59 to latch in incoming data on the data bus DQ.

In order to ensure proper timing of the various memory operations performed by the SLDRAM modules 11 a . . . 11 n, the FIG. 2 circuit must be synchronized to ensure the incoming data is properly clocked in by the clock signals CCLK and DCLK To this end, and in accordance with the invention, a 2^(N) bit synchronizing pattern is applied to each of the data input paths CAO-9 and FLAG while the data pattern is sampled in latches 23 and 25 by the delayed clock signal CCLK. The control logic circuit 21 steps through all possible delay positions of ring delays 27 and 29 as the data sampling is performed and stores patterns representing which delay values for the ring delays 27 and 29 provide for a correct sampling and recognition of the 2^(N) bit pattern. In this manner, control logic circuit 21 establishes an “eye” or “window” of acceptable delays for each of the ring delays 27 for the command data paths CAO-9 and for ring delay 29 for the FLAG input path. Once a “window” of acceptable delays is found for each of the ring delays 27 and for the ring delay 29, the control logic circuit 21 determines the “best” delay value as that value which is approximately in the middle of the window.

To illustrate the calibration process we will discuss calibration of the data appearing on the FLAG path, it being understood that the same calibration process is also carried out on each path of the command bus CAO-9 and each receive path of the data bus DQ. FIG. 3 illustrates a simplified timing diagram of the clock signal CCLK, the FLAG signal, the command bus signal CMD, a data bus signal DQ/DBUS and a data strobe signal DCLK. As shown, four bits of data on a DQ path of the data bus (DBUS) are clocked in on four sequential positive and negative going transitions of the data clock signal DCLK after an initial PREAMBLE portion of DCLK appears. The data present on the command signal paths CAO-9 and on the FLAG path is clocked in by the command clock signal CCLK.

Returning to FIG. 2, it can be seen that the data entering on the FLAG signal path passes through ring delay circuit 29 and is latched in latch 25 by the command clock signal CCLK. This data is then serially applied to control logic circuit 21. During the calibration period, and in accordance with the invention, a known 2^(N) bit synchronization pattern is applied to the FLAG path by memory controller 13 (FIG. 1), together with the free running clock signal CCLK. The control logic circuit knows what the 2^(N) bit calibration pattern is as it is stored and/or generated therein, and reads the repeating pattern bit-by-bit from latch 25. When doing so, the control logic circuit 21 first sets ring delay 29 for the FLAG path to one known delay setting. The control logic circuit 21 then examines the bit pattern sequentially received from latch 25 to see if it matches the known synchronization bit pattern. If the timing of the synchronization pattern data on the FLAG path is not aligned with the transitions of the CCLK signal, the correct bit pattern is not recognized at the output of latch 25 and the control logic circuit 21 will adjust ring delay 29 to the next delay setting, offset by a given amount from the prior delay setting of ring delay 29. Control logic circuit 21 will again continue to examine the synchronization pattern emerging from latch 25 to see if it matches the synchronization bit pattern. If not, it continues to increment the delay value of the ring delay 29 and repeat the sampling and examination process until the correct 2^(N) bit is recognized. In actuality, rather than stopping the calibration process when the correct synchronization bit pattern is recognized at the output of latch 25, the control logic circuit 21 will actually step through all possible delay values of ring delay 29 and keep track of which delays produced a proper recognition of the 2^(N) bit synchronization pattern. Then the control logic circuit 21 will select as a final delay value for ring delay 29, that value which is approximately centered between all delay values which produced a proper recognition of the 2^(N) bit synchronization pattern.

FIG. 4 illustrates the data envelope for consecutive bits of the 2^(N) bit synchronization pattern together with the clock signals CCLK which latch the data in latch 25. The relative timing of the data envelope and the control data clock CCLK is illustrated as ten possibilities CCLK 1 . . . 10, that is, ten possible delay values for ring delay 29. The beginning and end of the data envelope is where the data on the FLAG path is unstable which can lead to erroneous sampling of the data. As shown, reliable data capture occurs at the relative timing location C₄ through C₇, while unreliable data capture occurs at the relative timing locations C₁ . . . C₃ and C₈ . . . C₁₀. These are represented within control logic circuit 21 as delay values D₄ . . . D₇, where the 2^(N) bit synchronizing pattern was properly recognized. FIG. 5 illustrates how this is represented in control logic circuit 21 where delay values D₁ . . . D₃ and D₈ . . . D₁₀ show a “0” logic state representing that the 2^(N) bit synchronization pattern was not recognized and the logic state “1” for delay values D₄ . . . D₇, indicating a proper recognition of the 2^(N) bit synchronization pattern. It should be understood that although only 10 relative delay states of the data to the command clock signal CCLK are shown for simplicity, in actual practice there may be many more possible delay stages for ring delay 29 and the logic state pattern illustrated in FIG. 5.

Once the delay state pattern shown in FIG. 5 is developed by control logic circuit 21, it selects as a final delay for ring delay 29 a delay value which is approximately in the center of those delay values, e.g., D₄ . . . D₇, which produced a proper recognition of the 2^(N) bit synchronization pattern. In the example illustrated, the final delay would be selected as D₅ or D₆. Once this value is set for ring delay 29, the FLAG data path has been calibrated.

The same calibration procedure is also applied to each of the CMD data paths CAO-9 and to each of the data paths of the DQ bus, except for the latter, the data clock DCLK is used to latch the data in latch 59 which is present in each of the data paths of the DQ data bus.

As noted, an important aspect of the invention is the use of a 2^(N) bit pattern for the synchronization signal. Because the number of bit positions in the repeating pattern is even, the pattern will always synchronize on the same direction-going edge of the clock signal CCLK or DCLK, e.g., the positive-going edge, which removes ambiguity and simplifies the control logic circuit 21.

A circuit for generating the 2^(N) bit pattern, where N=4, to produce a repeating 16 bit pattern, is illustrated in FIG. 6. It includes a four stage shift register 151 having bit positions <0><1><2><3>, NOR gate 153 having three inputs respectively connected to the <0><1><2> outputs of shift register 151, an exclusive OR gate 155 having two inputs respectively connected to the output <3> of shift register 151 and the output of NOR gate 153, and an exclusive OR gate 157 having a pair of inputs respectively connected to the output of exclusive OR gate 155 and the first stage output <0> of shift register 151. The output of exclusive OR gate 157 is applied as an input to stage <0> of shift register 151. The clock signal CLK is applied to shift register 151. The shift register 151 can initially be seeded with all zeroes “0” at stages <0><1><2><3>and it will generate the repeating 16 bit pattern “1111010110010000.” This pattern is similar to the 15-bit pseudo random pattern described above, but includes an additional bit, e.g. a “0” added to the 15-bit pattern. In lieu of generating the repeating bit pattern with a circuit, the pattern can also be stored in the memory controller 13 (FIG. 1) and repeatedly read out during calibration.

The calibration of one data path as described above can also be performed with in phase and out of phase cross talk components applied to adjacent data pins and/or data paths. In this manner, calibration can be obtained under conditions which more closely replicate conditions of actual use. Thus, for example, when a particular data path, e.g., FLAG, is being calibrated with the 2^(N) bit synchronization pattern, the same pattern can be applied to adjacent data pins and/or paths, e.g., an adjacent path of the CAO-9 bus, in phase and/or out of phase.

As an example, when the data table of FIG. 5 is being constructed, adjacent data paths to the data path being calibrated, e.g., FLAG, may be fed, in phase, the same 2^(N) bit calibration synchronizing pattern, so that calibration is determined in the presence of in phase cross talk in adjacent data paths. Thereafter, the calibration process can be repeated for the path under calibration, e.g., FLAG, with adjacent data paths receiving an out of phase 2^(N) bit calibration pattern so that calibration is determined in the presence of out of phase cross talk on adjacent pins and/or data paths It is also possible to feed an in phase calibration signal to one adjacent data path and out of phase calibration signal to another adjacent data path to the one under calibration. Yet other possibilities are to apply in phase and out of phase calibration signals alternatively to all other data paths except the one currently under calibration. In all these possibilities for driving the other data paths, the control logic circuit 21 develops a table of the type shown in FIG. 5 showing which delays produce acceptable time alignments of the data on the path being calibrated with the clock signal (CCLK or DCLK as appropriate).

FIG. 7 shows one such exemplary set of tables for calibration of a given data path, e.g., FLAG, under conditions of: (A) in phase calibration signals applied to all other data paths; (B) out of phase calibration signals applied to all other data paths; and (C) alternating in phase and out of phase calibration signals applied to all other data paths. Once the control logic circuit 21 has developed the calibration tables for a given data path, e.g., FLAG, under the various possibilities of applying in phase and out of phase calibration patterns to other data paths, it will select a final delay value for the ring delay, e.g., ring delay 29 for the FLAG data path, which best represents a ring delay value in the center of each of the developed tables. In the example shown in the tables of FIG. 6, the selected value would likely be D₅ or D₆ which is in the delay range of each of the tables and is closest to the center of the delay for all tables. The selected delay is one which will provide adequate time alignment under all conditions of the application of in phase and out of phase calibration signals for the other data paths not currently under calibration.

It is also possible to calibrate several data paths simultaneously using the techniques described above with the remaining data paths not under calibration using in phase and/or out of phase calibration signals. For example, half of the data paths can be designated as “victims” and undergo simultaneous calibration, while the remaining half of the data paths can be designated as noise sources. Calibration would simultaneously occur on the “victim” data paths while the noise source data paths receive alternating in phase and out of phase calibration signals. After calibration of the “victims,” the “victim” and “noise source” pins and/or data paths would then be reversed and calibration now carried out on the new “victims” using the other data paths as noise sources as described above.

It is also possible to use the 2^(N) bit calibration pattern of the invention together with a 2 ^(N)−1 bit pattern to calibrate the data paths. With this technique, a table of acceptable delays for each of the bit patterns, similar to that of FIG. 5, is established and the final delay value is selected from a delay value approximately midway of the acceptable delays for both bit patterns.

An SLDRAM circuit containing the calibration structure and operating as described above may be used in a processor-based system of the type shown in FIG. 8. The processor-based system 90 comprises a processor 94, a memory circuit 96, and an I/O (input/output) device 92. The memory circuit 96 contains a SLDRAM memory circuit containing the calibration structure operating as described in accordance with the present invention. Memory other than SLDRAM may also be used. In addition, the processor 94 may itself be an integrated processor which utilizes on chip memory devices containing the calibration structure of the present invention.

In the preceding discussion, the apparatus and method of the invention has been described with regard to a memory device which clocks data (i.e., reads or writes data) twice per clock cycle: on both the rising and falling edges of the clock. However, the present invention may be used in any memory device in which calibration is performed, including devices which clock data once per clock cycle, for example on one of either the rising or falling edge of the clock.

While the invention has been described and illustrated with reference to exemplary embodiments, many variations can be made and equivalents substituted without departing from the spirit or scope of the invention. Accordingly, the invention is not to be understood as being limited by the foregoing description, but is only limited by the scope of the appended claims. 

1-94. (canceled)
 95. A device for generating a training pattern for use in calibrating a memory device, comprising: an signal path for coupling to a command bus or a flag signal input of said memory device; and a pattern generator for generating a 2^(N) bit repeating pattern on said signal path; wherein N is a positive integer and said 2^(N) bit repeating pattern comprises a predetermined additional bit appended to a (2^(N)−1) pseudo-random bit sequence.
 96. The device of claim 95, wherein said pattern generator comprises: a N-stage shift register, comprising: a shift register input; a shift register output, coupled to said signal path, for outputting said repeating bit pattern; and N shifting stages, configured to sequentially shift a bit present at said shift register input to said shift register output through each of said N shifting stages, said N shifting stages including a least significant stage 0 through a most significant stage N−1; a NOR gate having an output and N−1 inputs, each of said N−1 inputs respectively tapping said shift register at stage 1 through stage N−1; a first exclusive OR gate having an output and a first input coupled to said output of said NOR gate and a second input coupled to said shift register output; and a second exclusive OR gate having an output coupled to said shift register input and a first input coupled to said output of said first exclusive OR gate and a second input coupled to tap said shift register at stage
 0. 97. The device of claim 96, further comprising: a reset circuit, configured to set each stage of said shift register to a binary zero state.
 98. The device of claim 95, wherein N is equal to
 4. 99. The device of claim 95, wherein said device is a memory controller and further includes circuitry for communicating commands and data to at least one memory device.
 100. A memory device, comprising: a control circuit; N signal paths, wherein N is an integer of at least 1; N variable delay circuits; N latches; a data path; at least one memory array; a data circuit, coupled between and configure to transfer information between said data path and said at least one memory array, said data circuit also coupled to said control circuit; a clock path, coupled to supply a clock signal to said control circuit and said N latches; wherein said N signal paths are respectively coupled to said N variable delay elements, said N variable delay circuits are respectively coupled to said N latches, said N latches are each coupled to said control circuit; and said control circuit is configured to analyze a bit pattern at the output of said latch circuit and adjust the delay of said variable delay circuit to synchronize data on said data path with a clock signal on said clock path.
 101. The memory device of claim 100, wherein said N signal paths comprise: a command signal path, for communicating a commands from an external device to said memory device.
 102. The memory device of claim 100, wherein said N signal paths comprise: a plurality of command signal paths, forming a command bus for communicating commands from an external device to said memory device.
 103. The memory device of claim 102, wherein a number of said plurality of command signal paths is
 10. 104. The memory device of claim 100, wherein said N signal paths comprise: a flag signal path, for communicating a 1-bit flag signal to said memory device from an external device.
 105. A memory system, comprising: a memory controller, said memory controller comprising: a data path; M signal paths; and a pattern generator for generating a 2^(N) bit repeating pattern on at least one of said M signal paths; wherein N is a positive integer and M is an integer greater than or equal to 1; and a memory device, said memory device coupled to said memory controller via said data path and said M signal paths, said memory device comprising: a control circuit; M variable delay circuits; M latches; at least one memory array; a data circuit, coupled between and configure to transfer information between said data path and said at least one memory array, said data circuit also coupled to said control circuit; a clock path, coupled to supply a clock signal to said control circuit and said M latches; wherein said M signal paths are respectively coupled to said M variable delay elements, said M variable delay circuits are respectively coupled to said M latches, said M latches are each coupled to said control circuit; and said control circuit is configured to analyze a bit pattern at the output of said latch circuit and adjust the delay of said variable delay circuit to synchronize data on said data path with a clock signal on said clock path.
 106. The system of claim 105, wherein said pattern generator comprises: a N-stage shift register, comprising: a shift register input; a shift register output, coupled to said signal path, for outputting said repeating bit pattern; and N shifting stages, configured to sequentially shift a bit present at said shift register input to said shift register output through each of said N shifting stages, said N shifting stages including a least significant stage 0 through a most. significant stage N−1; a NOR gate having an output and N−1 inputs, each of said N−1 inputs respectively tapping said shift register at stage 1 through stage N−1; a first exclusive OR gate having an output and a first input coupled to said output of said NOR gate and a second input coupled to said shift register output; and a second exclusive OR gate having an output coupled to said shift register input and a first input coupled to said output of said first exclusive OR gate and a second input coupled to tap said shift register at stage
 0. 107. The system of claim 106, wherein said pattern generator further comprises: a reset circuit, configured to set each stage of said shift register to a binary zero state.
 108. The system of claim 105, wherein N is equal to
 4. 109. The system of claim 105, wherein said M signal paths comprise a plurality of command paths forming a command bus.
 110. The system of claim 105, wherein said M signal paths comprise a flag signal path for communicating a 1-bit flag between said memory controller and said memory device. 